/********************************************************************
 * Copyright (C) 2013-2014 Texas Instruments Incorporated.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
#ifndef CSLR_CM3NVIC_H_
#define CSLR_CM3NVIC_H_

#ifdef __cplusplus
extern "C"
{
#endif
#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>


/**************************************************************************
* Register Overlay Structure for __ALL__
**************************************************************************/
typedef struct {
    volatile Uint32 INTERRUPT_CONTROLLER_TYPE;
    volatile Uint32 AUXILIARY_CONTROL;
    volatile Uint8  RSVD0[4];
    volatile Uint32 SYSTICK_CONTROL_AND_STATUS;
    volatile Uint32 SYSTICK_RELOAD_VALUE;
    volatile Uint32 SYSTICK_CURRENT_VALUE;
    volatile Uint32 SYSTICK_CALIBRATION_VALUE;
    volatile Uint8  RSVD1[224];
    volatile Uint32 EXTERNAL_INTERRUPT_SETEN_0_31;
    volatile Uint32 EXTERNAL_INTERRUPT_SETEN_32_63;
    volatile Uint32 EXTERNAL_INTERRUPT_SETEN_64_95;
    volatile Uint8  RSVD2[116];
    volatile Uint32 EXTERNAL_INTERRUPT_CLREN_0_31;
    volatile Uint32 EXTERNAL_INTERRUPT_CLREN_32_63;
    volatile Uint32 EXTERNAL_INTERRUPT_CLREN_64_95;
    volatile Uint8  RSVD3[116];
    volatile Uint32 EXTERNAL_INTERRUPT_SETPEND_0_31;
    volatile Uint32 EXTERNAL_INTERRUPT_SETPEND_32_63;
    volatile Uint32 EXTERNAL_INTERRUPT_SETPEND_64_95;
    volatile Uint8  RSVD4[116];
    volatile Uint32 EXTERNAL_INTERRUPT_CLRPEND_0_31;
    volatile Uint32 EXTERNAL_INTERRUPT_CLRPEND_32_63;
    volatile Uint32 EXTERNAL_INTERRUPT_CLRPEND_64_95;
    volatile Uint8  RSVD5[116];
    volatile Uint32 EXTERNAL_INTERRUPT_ACTIVE_0_31;
    volatile Uint32 EXTERNAL_INTERRUPT_ACTIVE_32_63;
    volatile Uint32 EXTERNAL_INTERRUPT_ACTIVE_64_95;
    volatile Uint8  RSVD6[244];
    volatile Uint32 EXTERNAL_INT_PRIORITY_LEVEL[16];
    volatile Uint8  RSVD7[2240];
    volatile Uint32 CPU_ID_BASE_REGISTER;
    volatile Uint32 INTERRUPT_CONTROL_AND_STATE;
    volatile Uint32 VECTOR_TABLE_OFFSET;
    volatile Uint32 APPLICATION_INT_AND_RESET_CONTROL;
    volatile Uint32 SYSTEM_CONTROL;
    volatile Uint32 CONFIGURATION_CONTROL;
    volatile Uint32 SYSTEM_EXCEPTION_PRIORITY_LEVEL[3];
    volatile Uint32 SYSTEM_HANDLER_CONTROL_AND_STATE;
    volatile Uint32 CONFIGURABLE_FAULT_STATUS;
    volatile Uint32 HARD_FAULT_STATUS;
    volatile Uint32 DEBUG_FAULT_STATUS;
    volatile Uint32 MEMORY_MANAGE_ADDRESS;
    volatile Uint32 BUS_FAULT_MANAGE_ADDRESS;
    volatile Uint32 AUXILIARY_FAULT_STATUS;
    volatile Uint8  RSVD8[80];
    volatile Uint32 MPU_TYPE;
    volatile Uint32 MPU_CONTROL;
    volatile Uint32 MPU_REGION_NUMBER;
    volatile Uint32 MPU_REGION_BASE_ADDRESS;
    volatile Uint32 MPU_REGION_BASE_ATTRIBUTE_AND_SIZE;
    volatile Uint32 MPU_ALIAS[6];
    volatile Uint8  RSVD9[52];
    volatile Uint32 DEBUG_HALTING_CONTROL_AND_STATUS;
    volatile Uint32 DEBUG_CORE_REGISTER_SELECTOR;
    volatile Uint32 DEBUG_CORE_REGISTER_DATA;
    volatile Uint32 DEBUG_EXCEPTION_AND_MONITOR_CONTROL;
    volatile Uint8  RSVD10[256];
    volatile Uint32 SOFTWARE_TRIGGER_INTERRUPT;
    volatile Uint8  RSVD11[204];
    volatile Uint32 NVIC_PERIPHERAL_ID_4;
    volatile Uint32 NVIC_PERIPHERAL_ID_5;
    volatile Uint32 NVIC_PERIPHERAL_ID_6;
    volatile Uint32 NVIC_PERIPHERAL_ID_7;
    volatile Uint32 NVIC_PERIPHERAL_ID_0;
    volatile Uint32 NVIC_PERIPHERAL_ID_1;
    volatile Uint32 NVIC_PERIPHERAL_ID_2;
    volatile Uint32 NVIC_PERIPHERAL_ID_3;
    volatile Uint32 NVIC_COMPONENT_ID_0;
    volatile Uint32 NVIC_COMPONENT_ID_1;
    volatile Uint32 NVIC_COMPONENT_ID_2;
    volatile Uint32 NVIC_COMPONENT_ID_3;
} CSL_Cm3NvicRegs;


/**************************************************************************
* Register Macros
**************************************************************************/

/* Nber of interrupt inputs in step of 32: 0 =1 to 32 1 = 33 to 64 ... */
#define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE                   (0x4U)

/* AUXILIARY_CONTROL */
#define CSL_CM3NVIC_AUXILIARY_CONTROL                           (0x8U)

/* SYSTICK_CONTROL_AND_STATUS */
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS                  (0x10U)

/* SYSTICK_RELOAD_VALUE */
#define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE                        (0x14U)

/* SYSTICK_CURRENT_VALUE */
#define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE                       (0x18U)

/* SYSTICK_CALIBRATION_VALUE */
#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE                   (0x1CU)

/* Interrupt set enable bits. For write operation: 1 = enable interrupt 0 = no
 * effect. For read operation: 1 = enable interrupt 0 = disable interrupt
 * Writing 0 to a SETENA bit has no effect. Reading the bit returns its
 * current enable state. Reset clears the SETENA fields. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31               (0x100U)

/* Interrupt set enable bits. For write operation: 1 = enable interrupt 0 = no
 * effect. For read operation: 1 = enable interrupt 0 = disable interrupt
 * Writing 0 to a SETENA bit has no effect. Reading the bit returns its
 * current enable state. Reset clears the SETENA fields. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63              (0x104U)

/* Interrupt set enable bits. For write operation: 1 = enable interrupt 0 = no
 * effect. For read operation: 1 = enable interrupt 0 = disable interrupt
 * Writing 0 to a SETENA bit has no effect. Reading the bit returns its
 * current enable state. Reset clears the SETENA fields. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95              (0x108U)

/* Interrupt clear-enable bits. For write operation: 1 = disable interrupt 0 =
 * no effect. For read operation: 1 = enable interrupt 0 = disable interrupt.
 * Writing 0 to a CLRENA bit has no effect. Reading the bit returns its
 * current enable state. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31               (0x180U)

/* Interrupt set enable bits. For write operation: 1 = enable interrupt 0 = no
 * effect. For read operation: 1 = enable interrupt 0 = disable interrupt
 * Writing 0 to a SETENA bit has no effect. Reading the bit returns its
 * current enable state. Reset clears the SETENA fields. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63              (0x184U)

/* Interrupt clear-enable bits. For write operation: 1 = disable interrupt 0 =
 * no effect. For read operation: 1 = enable interrupt 0 = disable interrupt.
 * Writing 0 to a CLRENA bit has no effect. Reading the bit returns its
 * current enable state. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95              (0x188U)

/* Interrupt set-pending bits: 1 = pend the corresponding interrupt 0 =
 * corresponding interrupt not pending. Writing 0 to a SETPEND bit has no
 * effect. Reading the bit returns its current state. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31             (0x200U)

/* Interrupt set-pending bits: 1 = pend the corresponding interrupt 0 =
 * corresponding interrupt not pending. Writing 0 to a SETPEND bit has no
 * effect. Reading the bit returns its current state. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63            (0x204U)

/* Interrupt set-pending bits: 1 = pend the corresponding interrupt 0 =
 * corresponding interrupt not pending. Writing 0 to a SETPEND bit has no
 * effect. Reading the bit returns its current state. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95            (0x208U)

/* Interrupt clear-pending bits: 1 = clear pending interrupt 0 = do not clear
 * pending interrupt. Writing 0 to a CLRPEND bit has no effect. Reading the
 * bit returns its current state. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31             (0x280U)

/* Interrupt clear-pending bits: 1 = clear pending interrupt 0 = do not clear
 * pending interrupt. Writing 0 to a CLRPEND bit has no effect. Reading the
 * bit returns its current state. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63            (0x284U)

/* Interrupt clear-pending bits: 1 = clear pending interrupt 0 = do not clear
 * pending interrupt. Writing 0 to a CLRPEND bit has no effect. Reading the
 * bit returns its current state. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95            (0x288U)

/* Interrupt active flags: 1 = interrupt active or pre-empted and stacked 0 =
 * interrupt not active or stacked. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31              (0x300U)

/* Interrupt active flags: 1 = interrupt active or pre-empted and stacked 0 =
 * interrupt not active or stacked. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63             (0x304U)

/* Interrupt active flags: 1 = interrupt active or pre-empted and stacked 0 =
 * interrupt not active or stacked. */
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95             (0x308U)

/* Use the Interrupt Priority Registers to assign a priority from 0 to 255 to
 * each of the available interrupts. 0 is the highest priority, and 255 is the
 * lowest. The priority registers are stored with the Most Significant Bit
 * (MSB) first. This means that if there are four bits of priority, the
 * priority value is stored in bits [7:4] of the byte. However, if there are
 * three bits of priority, the priority value is stored in bits [7:5] of the
 * byte. This means that an application can work even if it does not know how
 * many priorities are possible. */
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL(i)              (0x400U + ((i) * (0x4U)))

/* CPU_ID_BASE_REGISTER */
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER                        (0xD00U)

/* INTERRUPT_CONTROL_AND_STATE */
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE                 (0xD04U)

/* VECTOR_TABLE_OFFSET */
#define CSL_CM3NVIC_VECTOR_TABLE_OFFSET                         (0xD08U)

/* APPLICATION_INT_AND_RESET_CONTROL */
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL           (0xD0CU)

/* SYSTEM_CONTROL */
#define CSL_CM3NVIC_SYSTEM_CONTROL                              (0xD10U)

/* CONFIGURATION_CONTROL */
#define CSL_CM3NVIC_CONFIGURATION_CONTROL                       (0xD14U)

/* SYSTEM_EXCEPTION_PRIORITY_LEVEL */
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL(i)          (0xD18U + ((i) * (0x4U)))

/* SYSTEM_HANDLER_CONTROL_AND_STATE */
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE            (0xD24U)

/* CONFIGURABLE_FAULT_STATUS */
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS                   (0xD28U)

/* HARD_FAULT_STATUS */
#define CSL_CM3NVIC_HARD_FAULT_STATUS                           (0xD2CU)

/* DEBUG_FAULT_STATUS */
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS                          (0xD30U)

/* MEMORY_MANAGE_ADDRESS */
#define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS                       (0xD34U)

/* BUS_FAULT_MANAGE_ADDRESS */
#define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS                    (0xD38U)

/* AUXILIARY_FAULT_STATUS */
#define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS                      (0xD3CU)

/* MPU_TYPE */
#define CSL_CM3NVIC_MPU_TYPE                                    (0xD90U)

/* MPU_CONTROL */
#define CSL_CM3NVIC_MPU_CONTROL                                 (0xD94U)

/* MPU_REGION_NUMBER */
#define CSL_CM3NVIC_MPU_REGION_NUMBER                           (0xD98U)

/* MPU_REGION_BASE_ADDRESS */
#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS                     (0xD9CU)

/* MPU_REGION_BASE_ATTRIBUTE_AND_SIZE */
#define CSL_CM3NVIC_MPU_REGION_BASE_ATTRIBUTE_AND_SIZE          (0xDA0U)

/* MPU_ALIAS */
#define CSL_CM3NVIC_MPU_ALIAS(i)                                (0xDA4U + ((i) * (0x4U)))

/* DEBUG_HALTING_CONTROL_AND_STATUS */
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS            (0xDF0U)

/* DEBUG_CORE_REGISTER_SELECTOR */
#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR                (0xDF4U)

/* DEBUG_CORE_REGISTER_DATA */
#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA                    (0xDF8U)

/* DEBUG_EXCEPTION_AND_MONITOR_CONTROL */
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL         (0xDFCU)

/* SOFTWARE_TRIGGER_INTERRUPT */
#define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT                  (0xF00U)

/* NVIC_PERIPHERAL_ID_4 */
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4                        (0xFD0U)

/* NVIC_PERIPHERAL_ID_5 */
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5                        (0xFD4U)

/* NVIC_PERIPHERAL_ID_6 */
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6                        (0xFD8U)

/* NVIC_PERIPHERAL_ID_7 */
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7                        (0xFDCU)

/* NVIC_PERIPHERAL_ID_0 */
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0                        (0xFE0U)

/* NVIC_PERIPHERAL_ID_1 */
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1                        (0xFE4U)

/* NVIC_PERIPHERAL_ID_2 */
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2                        (0xFE8U)

/* NVIC_PERIPHERAL_ID_3 */
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3                        (0xFECU)

/* NVIC_COMPONENT_ID_0 */
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_0                         (0xFF0U)

/* NVIC_COMPONENT_ID_1 */
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_1                         (0xFF4U)

/* NVIC_COMPONENT_ID_2 */
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_2                         (0xFF8U)

/* NVIC_COMPONENT_ID_3 */
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_3                         (0xFFCU)


/**************************************************************************
* Field Definition Macros
**************************************************************************/

/* INTERRUPT_CONTROLLER_TYPE */

#define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE_INTLINESNUM_MASK  (0x0000001FU)
#define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE_INTLINESNUM_SHIFT  (0U)
#define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE_INTLINESNUM_RESETVAL  (0x00000003U)
#define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE_INTLINESNUM_MAX   (0x0000001fU)

#define CSL_CM3NVIC_INTERRUPT_CONTROLLER_TYPE_RESETVAL          (0x00000003U)

/* AUXILIARY_CONTROL */

#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISMCYCINT_MASK           (0x00000001U)
#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISMCYCINT_SHIFT          (0U)
#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISMCYCINT_RESETVAL       (0x00000000U)
#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISMCYCINT_MAX            (0x00000001U)

#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISDEFWBUF_MASK           (0x00000002U)
#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISDEFWBUF_SHIFT          (1U)
#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISDEFWBUF_RESETVAL       (0x00000000U)
#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISDEFWBUF_MAX            (0x00000001U)

#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISFOLD_MASK              (0x00000004U)
#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISFOLD_SHIFT             (2U)
#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISFOLD_RESETVAL          (0x00000000U)
#define CSL_CM3NVIC_AUXILIARY_CONTROL_DISFOLD_MAX               (0x00000001U)

#define CSL_CM3NVIC_AUXILIARY_CONTROL_RESETVAL                  (0x00000000U)

/* SYSTICK_CONTROL_AND_STATUS */

#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_ENABLE_MASK      (0x00000001U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_ENABLE_SHIFT     (0U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_ENABLE_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_ENABLE_MAX       (0x00000001U)

#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_TICKINT_MASK     (0x00000002U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_TICKINT_SHIFT    (1U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_TICKINT_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_TICKINT_MAX      (0x00000001U)

#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_CLKSOURCE_MASK   (0x00000004U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_CLKSOURCE_SHIFT  (2U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_CLKSOURCE_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_CLKSOURCE_MAX    (0x00000001U)

#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_COUNTFLAG_MASK   (0x00010000U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_COUNTFLAG_SHIFT  (16U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_COUNTFLAG_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_COUNTFLAG_MAX    (0x00000001U)

#define CSL_CM3NVIC_SYSTICK_CONTROL_AND_STATUS_RESETVAL         (0x00000000U)

/* SYSTICK_RELOAD_VALUE */

#define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE_RELOAD_MASK            (0x00FFFFFFU)
#define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE_RELOAD_SHIFT           (0U)
#define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE_RELOAD_RESETVAL        (0x00000000U)
#define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE_RELOAD_MAX             (0x00ffffffU)

#define CSL_CM3NVIC_SYSTICK_RELOAD_VALUE_RESETVAL               (0x00000000U)

/* SYSTICK_CURRENT_VALUE */

#define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE_CURRENT_MASK          (0x00000001U)
#define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE_CURRENT_SHIFT         (0U)
#define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE_CURRENT_RESETVAL      (0x00000000U)
#define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE_CURRENT_MAX           (0x00000001U)

#define CSL_CM3NVIC_SYSTICK_CURRENT_VALUE_RESETVAL              (0x00000000U)

/* SYSTICK_CALIBRATION_VALUE */

#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_TENMS_MASK        (0x00FFFFFFU)
#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_TENMS_SHIFT       (0U)
#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_TENMS_RESETVAL    (0x00000000U)
#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_TENMS_MAX         (0x00ffffffU)

#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_NOREF_MASK        (0x80000000U)
#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_NOREF_SHIFT       (31U)
#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_NOREF_RESETVAL    (0x00000000U)
#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_NOREF_MAX         (0x00000001U)

#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_SKEW_MASK         (0x40000000U)
#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_SKEW_SHIFT        (30U)
#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_SKEW_RESETVAL     (0x00000000U)
#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_SKEW_MAX          (0x00000001U)

#define CSL_CM3NVIC_SYSTICK_CALIBRATION_VALUE_RESETVAL          (0x00000000U)

/* EXTERNAL_INTERRUPT_SETEN_0_31 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA0_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA0_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA0_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA0_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA1_MASK  (0x00000002U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA1_SHIFT  (1U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA1_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA1_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA2_MASK  (0x00000004U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA2_SHIFT  (2U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA2_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA2_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA3_MASK  (0x00000008U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA3_SHIFT  (3U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA3_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA3_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA4_MASK  (0x00000010U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA4_SHIFT  (4U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA4_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA4_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA5_MASK  (0x00000020U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA5_SHIFT  (5U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA5_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA5_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA6_MASK  (0x00000040U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA6_SHIFT  (6U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA6_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA6_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA7_MASK  (0x00000080U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA7_SHIFT  (7U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA7_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA7_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA8_MASK  (0x00000100U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA8_SHIFT  (8U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA8_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA8_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA9_MASK  (0x00000200U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA9_SHIFT  (9U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA9_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA9_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA10_MASK  (0x00000400U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA10_SHIFT  (10U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA10_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA10_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA11_MASK  (0x00000800U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA11_SHIFT  (11U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA11_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA11_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA12_MASK  (0x00001000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA12_SHIFT  (12U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA12_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA12_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA13_MASK  (0x00002000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA13_SHIFT  (13U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA13_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA13_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA14_MASK  (0x00004000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA14_SHIFT  (14U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA14_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA14_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA15_MASK  (0x00008000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA15_SHIFT  (15U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA15_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA15_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA16_MASK  (0x00010000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA16_SHIFT  (16U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA16_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA16_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA17_MASK  (0x00020000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA17_SHIFT  (17U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA17_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA17_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA18_MASK  (0x00040000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA18_SHIFT  (18U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA18_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA18_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA19_MASK  (0x00080000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA19_SHIFT  (19U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA19_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA19_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA20_MASK  (0x00100000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA20_SHIFT  (20U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA20_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA20_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA21_MASK  (0x00200000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA21_SHIFT  (21U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA21_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA21_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA22_MASK  (0x00400000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA22_SHIFT  (22U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA22_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA22_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA23_MASK  (0x00800000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA23_SHIFT  (23U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA23_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA23_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA24_MASK  (0x01000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA24_SHIFT  (24U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA24_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA24_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA25_MASK  (0x02000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA25_SHIFT  (25U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA25_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA25_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA26_MASK  (0x04000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA26_SHIFT  (26U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA26_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA26_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA27_MASK  (0x08000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA27_SHIFT  (27U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA27_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA27_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA28_MASK  (0x10000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA28_SHIFT  (28U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA28_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA28_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA29_MASK  (0x20000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA29_SHIFT  (29U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA29_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA29_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA30_MASK  (0x40000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA30_SHIFT  (30U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA30_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA30_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA31_MASK  (0x80000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA31_SHIFT  (31U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA31_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_SETENA31_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_0_31_RESETVAL      (0x00000000U)

/* EXTERNAL_INTERRUPT_SETEN_32_63 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA32_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA32_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA32_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA32_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA33_MASK  (0x00000002U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA33_SHIFT  (1U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA33_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA33_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA34_MASK  (0x00000004U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA34_SHIFT  (2U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA34_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA34_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA35_MASK  (0x00000008U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA35_SHIFT  (3U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA35_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA35_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA36_MASK  (0x00000010U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA36_SHIFT  (4U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA36_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA36_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA37_MASK  (0x00000020U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA37_SHIFT  (5U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA37_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA37_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA38_MASK  (0x00000040U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA38_SHIFT  (6U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA38_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA38_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA39_MASK  (0x00000080U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA39_SHIFT  (7U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA39_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA39_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA40_MASK  (0x00000100U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA40_SHIFT  (8U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA40_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA40_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA41_MASK  (0x00000200U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA41_SHIFT  (9U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA41_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA41_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA42_MASK  (0x00000400U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA42_SHIFT  (10U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA42_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA42_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA43_MASK  (0x00000800U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA43_SHIFT  (11U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA43_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA43_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA44_MASK  (0x00001000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA44_SHIFT  (12U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA44_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA44_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA45_MASK  (0x00002000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA45_SHIFT  (13U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA45_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA45_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA46_MASK  (0x00004000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA46_SHIFT  (14U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA46_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA46_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA47_MASK  (0x00008000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA47_SHIFT  (15U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA47_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA47_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA48_MASK  (0x00010000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA48_SHIFT  (16U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA48_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA48_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA49_MASK  (0x00020000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA49_SHIFT  (17U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA49_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA49_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA50_MASK  (0x00040000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA50_SHIFT  (18U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA50_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA50_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA51_MASK  (0x00080000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA51_SHIFT  (19U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA51_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA51_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA52_MASK  (0x00100000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA52_SHIFT  (20U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA52_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA52_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA53_MASK  (0x00200000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA53_SHIFT  (21U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA53_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA53_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA54_MASK  (0x00400000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA54_SHIFT  (22U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA54_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA54_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA55_MASK  (0x00800000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA55_SHIFT  (23U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA55_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA55_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA56_MASK  (0x01000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA56_SHIFT  (24U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA56_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA56_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA57_MASK  (0x02000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA57_SHIFT  (25U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA57_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA57_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA58_MASK  (0x04000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA58_SHIFT  (26U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA58_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA58_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA59_MASK  (0x08000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA59_SHIFT  (27U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA59_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA59_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA60_MASK  (0x10000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA60_SHIFT  (28U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA60_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA60_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA61_MASK  (0x20000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA61_SHIFT  (29U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA61_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA61_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA62_MASK  (0x40000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA62_SHIFT  (30U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA62_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA62_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA63_MASK  (0x80000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA63_SHIFT  (31U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA63_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_SETENA63_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_32_63_RESETVAL     (0x00000000U)

/* EXTERNAL_INTERRUPT_SETEN_64_95 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95_SETENA64_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95_SETENA64_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95_SETENA64_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95_SETENA64_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETEN_64_95_RESETVAL     (0x00000000U)

/* EXTERNAL_INTERRUPT_CLREN_0_31 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA0_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA0_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA0_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA0_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA1_MASK  (0x00000002U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA1_SHIFT  (1U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA1_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA1_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA2_MASK  (0x00000004U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA2_SHIFT  (2U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA2_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA2_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA3_MASK  (0x00000008U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA3_SHIFT  (3U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA3_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA3_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA4_MASK  (0x00000010U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA4_SHIFT  (4U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA4_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA4_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA5_MASK  (0x00000020U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA5_SHIFT  (5U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA5_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA5_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA6_MASK  (0x00000040U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA6_SHIFT  (6U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA6_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA6_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA7_MASK  (0x00000080U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA7_SHIFT  (7U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA7_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA7_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA8_MASK  (0x00000100U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA8_SHIFT  (8U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA8_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA8_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA9_MASK  (0x00000200U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA9_SHIFT  (9U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA9_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA9_MAX   (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA10_MASK  (0x00000400U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA10_SHIFT  (10U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA10_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA10_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA11_MASK  (0x00000800U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA11_SHIFT  (11U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA11_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA11_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA12_MASK  (0x00001000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA12_SHIFT  (12U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA12_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA12_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA13_MASK  (0x00002000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA13_SHIFT  (13U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA13_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA13_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA14_MASK  (0x00004000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA14_SHIFT  (14U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA14_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA14_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA15_MASK  (0x00008000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA15_SHIFT  (15U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA15_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA15_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA16_MASK  (0x00010000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA16_SHIFT  (16U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA16_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA16_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA17_MASK  (0x00020000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA17_SHIFT  (17U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA17_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA17_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA18_MASK  (0x00040000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA18_SHIFT  (18U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA18_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA18_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA19_MASK  (0x00080000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA19_SHIFT  (19U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA19_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA19_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA20_MASK  (0x00100000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA20_SHIFT  (20U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA20_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA20_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA21_MASK  (0x00200000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA21_SHIFT  (21U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA21_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA21_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA22_MASK  (0x00400000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA22_SHIFT  (22U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA22_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA22_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA23_MASK  (0x00800000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA23_SHIFT  (23U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA23_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA23_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA24_MASK  (0x01000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA24_SHIFT  (24U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA24_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA24_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA25_MASK  (0x02000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA25_SHIFT  (25U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA25_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA25_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA26_MASK  (0x04000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA26_SHIFT  (26U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA26_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA26_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA27_MASK  (0x08000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA27_SHIFT  (27U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA27_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA27_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA28_MASK  (0x10000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA28_SHIFT  (28U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA28_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA28_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA29_MASK  (0x20000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA29_SHIFT  (29U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA29_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA29_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA30_MASK  (0x40000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA30_SHIFT  (30U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA30_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA30_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA31_MASK  (0x80000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA31_SHIFT  (31U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA31_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_CLRENA31_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_0_31_RESETVAL      (0x00000000U)

/* EXTERNAL_INTERRUPT_CLREN_32_63 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA32_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA32_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA32_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA32_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA33_MASK  (0x00000002U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA33_SHIFT  (1U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA33_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA33_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA34_MASK  (0x00000004U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA34_SHIFT  (2U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA34_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA34_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA35_MASK  (0x00000008U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA35_SHIFT  (3U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA35_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA35_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA36_MASK  (0x00000010U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA36_SHIFT  (4U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA36_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA36_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA37_MASK  (0x00000020U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA37_SHIFT  (5U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA37_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA37_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA38_MASK  (0x00000040U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA38_SHIFT  (6U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA38_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA38_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA39_MASK  (0x00000080U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA39_SHIFT  (7U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA39_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA39_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA40_MASK  (0x00000100U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA40_SHIFT  (8U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA40_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA40_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA41_MASK  (0x00000200U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA41_SHIFT  (9U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA41_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA41_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA42_MASK  (0x00000400U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA42_SHIFT  (10U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA42_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA42_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA43_MASK  (0x00000800U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA43_SHIFT  (11U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA43_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA43_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA44_MASK  (0x00001000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA44_SHIFT  (12U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA44_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA44_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA45_MASK  (0x00002000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA45_SHIFT  (13U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA45_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA45_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA46_MASK  (0x00004000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA46_SHIFT  (14U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA46_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA46_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA47_MASK  (0x00008000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA47_SHIFT  (15U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA47_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA47_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA48_MASK  (0x00010000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA48_SHIFT  (16U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA48_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA48_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA49_MASK  (0x00020000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA49_SHIFT  (17U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA49_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA49_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA50_MASK  (0x00040000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA50_SHIFT  (18U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA50_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA50_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA51_MASK  (0x00080000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA51_SHIFT  (19U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA51_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA51_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA52_MASK  (0x00100000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA52_SHIFT  (20U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA52_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA52_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA53_MASK  (0x00200000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA53_SHIFT  (21U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA53_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA53_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA54_MASK  (0x00400000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA54_SHIFT  (22U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA54_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA54_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA55_MASK  (0x00800000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA55_SHIFT  (23U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA55_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA55_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA56_MASK  (0x01000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA56_SHIFT  (24U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA56_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA56_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA57_MASK  (0x02000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA57_SHIFT  (25U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA57_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA57_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA58_MASK  (0x04000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA58_SHIFT  (26U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA58_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA58_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA59_MASK  (0x08000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA59_SHIFT  (27U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA59_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA59_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA60_MASK  (0x10000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA60_SHIFT  (28U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA60_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA60_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA61_MASK  (0x20000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA61_SHIFT  (29U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA61_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA61_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA62_MASK  (0x40000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA62_SHIFT  (30U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA62_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA62_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA63_MASK  (0x80000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA63_SHIFT  (31U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA63_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_CLRENA63_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_32_63_RESETVAL     (0x00000000U)

/* EXTERNAL_INTERRUPT_CLREN_64_95 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95_CLRENA64_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95_CLRENA64_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95_CLRENA64_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95_CLRENA64_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLREN_64_95_RESETVAL     (0x00000000U)

/* EXTERNAL_INTERRUPT_SETPEND_0_31 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND0_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND0_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND0_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND0_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND1_MASK  (0x00000002U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND1_SHIFT  (1U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND1_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND1_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND2_MASK  (0x00000004U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND2_SHIFT  (2U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND2_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND2_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND3_MASK  (0x00000008U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND3_SHIFT  (3U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND3_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND3_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND4_MASK  (0x00000010U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND4_SHIFT  (4U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND4_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND4_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND5_MASK  (0x00000020U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND5_SHIFT  (5U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND5_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND5_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND6_MASK  (0x00000040U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND6_SHIFT  (6U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND6_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND6_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND7_MASK  (0x00000080U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND7_SHIFT  (7U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND7_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND7_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND8_MASK  (0x00000100U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND8_SHIFT  (8U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND8_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND8_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND9_MASK  (0x00000200U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND9_SHIFT  (9U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND9_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND9_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND10_MASK  (0x00000400U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND10_SHIFT  (10U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND10_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND10_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND11_MASK  (0x00000800U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND11_SHIFT  (11U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND11_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND11_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND12_MASK  (0x00001000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND12_SHIFT  (12U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND12_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND12_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND13_MASK  (0x00002000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND13_SHIFT  (13U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND13_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND13_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND14_MASK  (0x00004000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND14_SHIFT  (14U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND14_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND14_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND15_MASK  (0x00008000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND15_SHIFT  (15U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND15_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND15_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND16_MASK  (0x00010000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND16_SHIFT  (16U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND16_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND16_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND17_MASK  (0x00020000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND17_SHIFT  (17U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND17_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND17_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND18_MASK  (0x00040000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND18_SHIFT  (18U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND18_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND18_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND19_MASK  (0x00080000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND19_SHIFT  (19U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND19_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND19_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND20_MASK  (0x00100000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND20_SHIFT  (20U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND20_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND20_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND21_MASK  (0x00200000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND21_SHIFT  (21U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND21_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND21_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND22_MASK  (0x00400000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND22_SHIFT  (22U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND22_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND22_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND23_MASK  (0x00800000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND23_SHIFT  (23U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND23_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND23_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND24_MASK  (0x01000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND24_SHIFT  (24U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND24_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND24_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND25_MASK  (0x02000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND25_SHIFT  (25U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND25_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND25_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND26_MASK  (0x04000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND26_SHIFT  (26U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND26_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND26_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND27_MASK  (0x08000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND27_SHIFT  (27U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND27_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND27_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND28_MASK  (0x10000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND28_SHIFT  (28U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND28_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND28_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND29_MASK  (0x20000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND29_SHIFT  (29U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND29_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND29_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND30_MASK  (0x40000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND30_SHIFT  (30U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND30_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND30_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND31_MASK  (0x80000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND31_SHIFT  (31U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND31_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_SETPEND31_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_0_31_RESETVAL    (0x00000000U)

/* EXTERNAL_INTERRUPT_SETPEND_32_63 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND32_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND32_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND32_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND32_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND33_MASK  (0x00000002U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND33_SHIFT  (1U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND33_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND33_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND34_MASK  (0x00000004U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND34_SHIFT  (2U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND34_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND34_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND35_MASK  (0x00000008U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND35_SHIFT  (3U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND35_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND35_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND36_MASK  (0x00000010U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND36_SHIFT  (4U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND36_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND36_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND37_MASK  (0x00000020U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND37_SHIFT  (5U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND37_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND37_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND38_MASK  (0x00000040U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND38_SHIFT  (6U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND38_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND38_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND39_MASK  (0x00000080U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND39_SHIFT  (7U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND39_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND39_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND40_MASK  (0x00000100U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND40_SHIFT  (8U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND40_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND40_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND41_MASK  (0x00000200U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND41_SHIFT  (9U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND41_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND41_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND42_MASK  (0x00000400U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND42_SHIFT  (10U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND42_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND42_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND43_MASK  (0x00000800U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND43_SHIFT  (11U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND43_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND43_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND44_MASK  (0x00001000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND44_SHIFT  (12U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND44_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND44_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND45_MASK  (0x00002000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND45_SHIFT  (13U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND45_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND45_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND46_MASK  (0x00004000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND46_SHIFT  (14U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND46_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND46_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND47_MASK  (0x00008000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND47_SHIFT  (15U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND47_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND47_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND48_MASK  (0x00010000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND48_SHIFT  (16U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND48_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND48_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND49_MASK  (0x00020000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND49_SHIFT  (17U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND49_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND49_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND50_MASK  (0x00040000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND50_SHIFT  (18U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND50_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND50_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND51_MASK  (0x00080000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND51_SHIFT  (19U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND51_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND51_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND52_MASK  (0x00100000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND52_SHIFT  (20U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND52_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND52_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND53_MASK  (0x00200000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND53_SHIFT  (21U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND53_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND53_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND54_MASK  (0x00400000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND54_SHIFT  (22U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND54_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND54_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND55_MASK  (0x00800000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND55_SHIFT  (23U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND55_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND55_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND56_MASK  (0x01000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND56_SHIFT  (24U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND56_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND56_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND57_MASK  (0x02000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND57_SHIFT  (25U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND57_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND57_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND58_MASK  (0x04000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND58_SHIFT  (26U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND58_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND58_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND59_MASK  (0x08000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND59_SHIFT  (27U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND59_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND59_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND60_MASK  (0x10000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND60_SHIFT  (28U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND60_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND60_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND61_MASK  (0x20000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND61_SHIFT  (29U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND61_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND61_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND62_MASK  (0x40000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND62_SHIFT  (30U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND62_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND62_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND63_MASK  (0x80000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND63_SHIFT  (31U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND63_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_SETPEND63_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_32_63_RESETVAL   (0x00000000U)

/* EXTERNAL_INTERRUPT_SETPEND_64_95 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95_SETPEND64_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95_SETPEND64_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95_SETPEND64_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95_SETPEND64_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_SETPEND_64_95_RESETVAL   (0x00000000U)

/* EXTERNAL_INTERRUPT_CLRPEND_0_31 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND0_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND0_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND0_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND0_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND1_MASK  (0x00000002U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND1_SHIFT  (1U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND1_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND1_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND2_MASK  (0x00000004U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND2_SHIFT  (2U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND2_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND2_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND3_MASK  (0x00000008U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND3_SHIFT  (3U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND3_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND3_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND4_MASK  (0x00000010U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND4_SHIFT  (4U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND4_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND4_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND5_MASK  (0x00000020U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND5_SHIFT  (5U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND5_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND5_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND6_MASK  (0x00000040U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND6_SHIFT  (6U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND6_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND6_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND7_MASK  (0x00000080U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND7_SHIFT  (7U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND7_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND7_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND8_MASK  (0x00000100U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND8_SHIFT  (8U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND8_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND8_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND9_MASK  (0x00000200U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND9_SHIFT  (9U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND9_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND9_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND10_MASK  (0x00000400U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND10_SHIFT  (10U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND10_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND10_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND11_MASK  (0x00000800U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND11_SHIFT  (11U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND11_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND11_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND12_MASK  (0x00001000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND12_SHIFT  (12U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND12_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND12_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND13_MASK  (0x00002000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND13_SHIFT  (13U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND13_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND13_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND14_MASK  (0x00004000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND14_SHIFT  (14U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND14_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND14_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND15_MASK  (0x00008000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND15_SHIFT  (15U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND15_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND15_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND16_MASK  (0x00010000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND16_SHIFT  (16U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND16_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND16_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND17_MASK  (0x00020000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND17_SHIFT  (17U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND17_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND17_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND18_MASK  (0x00040000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND18_SHIFT  (18U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND18_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND18_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND19_MASK  (0x00080000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND19_SHIFT  (19U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND19_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND19_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND20_MASK  (0x00100000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND20_SHIFT  (20U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND20_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND20_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND21_MASK  (0x00200000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND21_SHIFT  (21U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND21_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND21_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND22_MASK  (0x00400000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND22_SHIFT  (22U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND22_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND22_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND23_MASK  (0x00800000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND23_SHIFT  (23U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND23_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND23_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND24_MASK  (0x01000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND24_SHIFT  (24U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND24_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND24_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND25_MASK  (0x02000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND25_SHIFT  (25U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND25_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND25_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND26_MASK  (0x04000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND26_SHIFT  (26U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND26_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND26_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND27_MASK  (0x08000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND27_SHIFT  (27U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND27_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND27_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND28_MASK  (0x10000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND28_SHIFT  (28U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND28_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND28_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND29_MASK  (0x20000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND29_SHIFT  (29U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND29_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND29_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND30_MASK  (0x40000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND30_SHIFT  (30U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND30_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND30_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND31_MASK  (0x80000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND31_SHIFT  (31U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND31_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_CLRPEND31_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_0_31_RESETVAL    (0x00000000U)

/* EXTERNAL_INTERRUPT_CLRPEND_32_63 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND32_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND32_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND32_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND32_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND33_MASK  (0x00000002U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND33_SHIFT  (1U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND33_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND33_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND34_MASK  (0x00000004U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND34_SHIFT  (2U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND34_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND34_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND35_MASK  (0x00000008U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND35_SHIFT  (3U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND35_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND35_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND36_MASK  (0x00000010U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND36_SHIFT  (4U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND36_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND36_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND37_MASK  (0x00000020U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND37_SHIFT  (5U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND37_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND37_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND38_MASK  (0x00000040U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND38_SHIFT  (6U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND38_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND38_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND39_MASK  (0x00000080U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND39_SHIFT  (7U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND39_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND39_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND40_MASK  (0x00000100U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND40_SHIFT  (8U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND40_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND40_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND41_MASK  (0x00000200U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND41_SHIFT  (9U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND41_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND41_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND42_MASK  (0x00000400U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND42_SHIFT  (10U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND42_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND42_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND43_MASK  (0x00000800U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND43_SHIFT  (11U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND43_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND43_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND44_MASK  (0x00001000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND44_SHIFT  (12U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND44_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND44_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND45_MASK  (0x00002000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND45_SHIFT  (13U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND45_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND45_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND46_MASK  (0x00004000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND46_SHIFT  (14U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND46_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND46_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND47_MASK  (0x00008000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND47_SHIFT  (15U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND47_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND47_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND48_MASK  (0x00010000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND48_SHIFT  (16U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND48_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND48_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND49_MASK  (0x00020000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND49_SHIFT  (17U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND49_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND49_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND50_MASK  (0x00040000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND50_SHIFT  (18U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND50_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND50_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND51_MASK  (0x00080000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND51_SHIFT  (19U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND51_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND51_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND52_MASK  (0x00100000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND52_SHIFT  (20U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND52_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND52_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND53_MASK  (0x00200000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND53_SHIFT  (21U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND53_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND53_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND54_MASK  (0x00400000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND54_SHIFT  (22U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND54_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND54_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND55_MASK  (0x00800000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND55_SHIFT  (23U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND55_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND55_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND56_MASK  (0x01000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND56_SHIFT  (24U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND56_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND56_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND57_MASK  (0x02000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND57_SHIFT  (25U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND57_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND57_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND58_MASK  (0x04000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND58_SHIFT  (26U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND58_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND58_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND59_MASK  (0x08000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND59_SHIFT  (27U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND59_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND59_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND60_MASK  (0x10000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND60_SHIFT  (28U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND60_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND60_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND61_MASK  (0x20000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND61_SHIFT  (29U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND61_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND61_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND62_MASK  (0x40000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND62_SHIFT  (30U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND62_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND62_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND63_MASK  (0x80000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND63_SHIFT  (31U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND63_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_CLRPEND63_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_32_63_RESETVAL   (0x00000000U)

/* EXTERNAL_INTERRUPT_CLRPEND_64_95 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95_CLRPEND64_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95_CLRPEND64_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95_CLRPEND64_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95_CLRPEND64_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_CLRPEND_64_95_RESETVAL   (0x00000000U)

/* EXTERNAL_INTERRUPT_ACTIVE_0_31 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE0_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE0_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE0_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE0_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE1_MASK  (0x00000002U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE1_SHIFT  (1U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE1_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE1_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE2_MASK  (0x00000004U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE2_SHIFT  (2U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE2_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE2_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE3_MASK  (0x00000008U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE3_SHIFT  (3U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE3_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE3_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE4_MASK  (0x00000010U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE4_SHIFT  (4U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE4_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE4_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE5_MASK  (0x00000020U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE5_SHIFT  (5U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE5_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE5_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE6_MASK  (0x00000040U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE6_SHIFT  (6U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE6_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE6_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE7_MASK  (0x00000080U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE7_SHIFT  (7U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE7_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE7_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE8_MASK  (0x00000100U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE8_SHIFT  (8U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE8_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE8_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE9_MASK  (0x00000200U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE9_SHIFT  (9U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE9_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE9_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE10_MASK  (0x00000400U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE10_SHIFT  (10U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE10_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE10_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE11_MASK  (0x00000800U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE11_SHIFT  (11U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE11_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE11_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE12_MASK  (0x00001000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE12_SHIFT  (12U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE12_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE12_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE13_MASK  (0x00002000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE13_SHIFT  (13U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE13_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE13_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE14_MASK  (0x00004000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE14_SHIFT  (14U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE14_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE14_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE15_MASK  (0x00008000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE15_SHIFT  (15U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE15_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE15_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE16_MASK  (0x00010000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE16_SHIFT  (16U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE16_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE16_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE17_MASK  (0x00020000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE17_SHIFT  (17U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE17_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE17_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE18_MASK  (0x00040000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE18_SHIFT  (18U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE18_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE18_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE19_MASK  (0x00080000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE19_SHIFT  (19U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE19_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE19_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE20_MASK  (0x00100000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE20_SHIFT  (20U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE20_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE20_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE21_MASK  (0x00200000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE21_SHIFT  (21U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE21_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE21_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE22_MASK  (0x00400000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE22_SHIFT  (22U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE22_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE22_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE23_MASK  (0x00800000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE23_SHIFT  (23U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE23_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE23_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE24_MASK  (0x01000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE24_SHIFT  (24U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE24_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE24_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE25_MASK  (0x02000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE25_SHIFT  (25U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE25_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE25_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE26_MASK  (0x04000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE26_SHIFT  (26U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE26_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE26_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE27_MASK  (0x08000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE27_SHIFT  (27U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE27_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE27_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE28_MASK  (0x10000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE28_SHIFT  (28U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE28_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE28_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE29_MASK  (0x20000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE29_SHIFT  (29U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE29_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE29_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE30_MASK  (0x40000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE30_SHIFT  (30U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE30_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE30_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE31_MASK  (0x80000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE31_SHIFT  (31U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE31_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_ACTIVE31_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_0_31_RESETVAL     (0x00000000U)

/* EXTERNAL_INTERRUPT_ACTIVE_32_63 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE32_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE32_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE32_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE32_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE33_MASK  (0x00000002U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE33_SHIFT  (1U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE33_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE33_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE34_MASK  (0x00000004U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE34_SHIFT  (2U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE34_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE34_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE35_MASK  (0x00000008U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE35_SHIFT  (3U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE35_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE35_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE36_MASK  (0x00000010U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE36_SHIFT  (4U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE36_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE36_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE37_MASK  (0x00000020U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE37_SHIFT  (5U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE37_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE37_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE38_MASK  (0x00000040U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE38_SHIFT  (6U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE38_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE38_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE39_MASK  (0x00000080U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE39_SHIFT  (7U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE39_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE39_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE40_MASK  (0x00000100U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE40_SHIFT  (8U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE40_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE40_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE41_MASK  (0x00000200U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE41_SHIFT  (9U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE41_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE41_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE42_MASK  (0x00000400U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE42_SHIFT  (10U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE42_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE42_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE43_MASK  (0x00000800U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE43_SHIFT  (11U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE43_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE43_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE44_MASK  (0x00001000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE44_SHIFT  (12U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE44_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE44_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE45_MASK  (0x00002000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE45_SHIFT  (13U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE45_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE45_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE46_MASK  (0x00004000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE46_SHIFT  (14U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE46_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE46_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE47_MASK  (0x00008000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE47_SHIFT  (15U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE47_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE47_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE48_MASK  (0x00010000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE48_SHIFT  (16U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE48_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE48_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE49_MASK  (0x00020000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE49_SHIFT  (17U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE49_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE49_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE50_MASK  (0x00040000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE50_SHIFT  (18U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE50_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE50_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE51_MASK  (0x00080000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE51_SHIFT  (19U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE51_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE51_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE52_MASK  (0x00100000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE52_SHIFT  (20U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE52_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE52_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE53_MASK  (0x00200000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE53_SHIFT  (21U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE53_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE53_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE54_MASK  (0x00400000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE54_SHIFT  (22U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE54_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE54_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE55_MASK  (0x00800000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE55_SHIFT  (23U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE55_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE55_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE56_MASK  (0x01000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE56_SHIFT  (24U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE56_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE56_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE57_MASK  (0x02000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE57_SHIFT  (25U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE57_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE57_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE58_MASK  (0x04000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE58_SHIFT  (26U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE58_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE58_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE59_MASK  (0x08000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE59_SHIFT  (27U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE59_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE59_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE60_MASK  (0x10000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE60_SHIFT  (28U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE60_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE60_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE61_MASK  (0x20000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE61_SHIFT  (29U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE61_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE61_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE62_MASK  (0x40000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE62_SHIFT  (30U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE62_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE62_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE63_MASK  (0x80000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE63_SHIFT  (31U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE63_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_ACTIVE63_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_32_63_RESETVAL    (0x00000000U)

/* EXTERNAL_INTERRUPT_ACTIVE_64_95 */

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95_ACTIVE64_MASK  (0x00000001U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95_ACTIVE64_SHIFT  (0U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95_ACTIVE64_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95_ACTIVE64_MAX  (0x00000001U)

#define CSL_CM3NVIC_EXTERNAL_INTERRUPT_ACTIVE_64_95_RESETVAL    (0x00000000U)

/* EXTERNAL_INT_PRIORITY_LEVEL */

#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI0_MASK       (0x000000FFU)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI0_SHIFT      (0U)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI0_RESETVAL   (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI0_MAX        (0x000000ffU)

#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI1_MASK       (0x0000FF00U)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI1_SHIFT      (8U)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI1_RESETVAL   (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI1_MAX        (0x000000ffU)

#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI2_MASK       (0x00FF0000U)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI2_SHIFT      (16U)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI2_RESETVAL   (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI2_MAX        (0x000000ffU)

#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI3_MASK       (0xFF000000U)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI3_SHIFT      (24U)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI3_RESETVAL   (0x00000000U)
#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_PRI3_MAX        (0x000000ffU)

#define CSL_CM3NVIC_EXTERNAL_INT_PRIORITY_LEVEL_RESETVAL        (0x00000000U)

/* CPU_ID_BASE_REGISTER */

#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_REVISION_MASK          (0x0000000FU)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_REVISION_SHIFT         (0U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_REVISION_RESETVAL      (0x00000000U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_REVISION_MAX           (0x0000000fU)

#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_PARTNO_MASK            (0x0000FFF0U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_PARTNO_SHIFT           (4U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_PARTNO_RESETVAL        (0x00000c23U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_PARTNO_MAX             (0x00000fffU)

#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_CONSTANT_MASK          (0x000F0000U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_CONSTANT_SHIFT         (16U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_CONSTANT_RESETVAL      (0x0000000fU)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_CONSTANT_MAX           (0x0000000fU)

#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_VARIANT_MASK           (0x00F00000U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_VARIANT_SHIFT          (20U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_VARIANT_RESETVAL       (0x00000002U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_VARIANT_MAX            (0x0000000fU)

#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_IMPLEMENTER_MASK       (0xFF000000U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_IMPLEMENTER_SHIFT      (24U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_IMPLEMENTER_RESETVAL   (0x00000041U)
#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_IMPLEMENTER_MAX        (0x000000ffU)

#define CSL_CM3NVIC_CPU_ID_BASE_REGISTER_RESETVAL               (0x412fc230U)

/* INTERRUPT_CONTROL_AND_STATE */

#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTACTIVE_MASK  (0x000003FFU)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTACTIVE_SHIFT  (0U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTACTIVE_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTACTIVE_MAX  (0x000003ffU)

#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_RETTOBASE_MASK  (0x00000400U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_RETTOBASE_SHIFT  (10U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_RETTOBASE_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_RETTOBASE_MAX   (0x00000001U)

#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTPENDING_MASK  (0x003FF800U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTPENDING_SHIFT  (11U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTPENDING_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_VECTPENDING_MAX  (0x000007ffU)

#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPENDING_MASK  (0x00400000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPENDING_SHIFT  (22U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPENDING_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPENDING_MAX  (0x00000001U)

#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPREEMPT_MASK  (0x00800000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPREEMPT_SHIFT  (23U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPREEMPT_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_ISRPREEMPT_MAX  (0x00000001U)

#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTCLR_MASK  (0x02000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTCLR_SHIFT  (25U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTCLR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTCLR_MAX   (0x00000001U)

#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTSET_MASK  (0x04000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTSET_SHIFT  (26U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTSET_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSTSET_MAX   (0x00000001U)

#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVCLR_MASK  (0x08000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVCLR_SHIFT  (27U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVCLR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVCLR_MAX   (0x00000001U)

#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVSET_MASK  (0x10000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVSET_SHIFT  (28U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVSET_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_PENDSVSET_MAX   (0x00000001U)

#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_NMIPENDSET_MASK  (0x80000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_NMIPENDSET_SHIFT  (31U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_NMIPENDSET_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_NMIPENDSET_MAX  (0x00000001U)

#define CSL_CM3NVIC_INTERRUPT_CONTROL_AND_STATE_RESETVAL        (0x00000000U)

/* VECTOR_TABLE_OFFSET */

#define CSL_CM3NVIC_VECTOR_TABLE_OFFSET_TBLOFF_MASK             (0xFFFFFF80U)
#define CSL_CM3NVIC_VECTOR_TABLE_OFFSET_TBLOFF_SHIFT            (7U)
#define CSL_CM3NVIC_VECTOR_TABLE_OFFSET_TBLOFF_RESETVAL         (0x00000000U)
#define CSL_CM3NVIC_VECTOR_TABLE_OFFSET_TBLOFF_MAX              (0x01ffffffU)

#define CSL_CM3NVIC_VECTOR_TABLE_OFFSET_RESETVAL                (0x00000000U)

/* APPLICATION_INT_AND_RESET_CONTROL */

#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTRESET_MASK  (0x00000001U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTRESET_SHIFT  (0U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTRESET_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTRESET_MAX  (0x00000001U)

#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTCLRACTIVE_MASK  (0x00000002U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTCLRACTIVE_SHIFT  (1U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTCLRACTIVE_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTCLRACTIVE_MAX  (0x00000001U)

#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_SYSRESETREQ_MASK  (0x00000004U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_SYSRESETREQ_SHIFT  (2U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_SYSRESETREQ_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_SYSRESETREQ_MAX  (0x00000001U)

#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_PRIGROUP_MASK  (0x00000700U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_PRIGROUP_SHIFT  (8U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_PRIGROUP_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_PRIGROUP_MAX  (0x00000007U)

#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_ENDIANESS_MASK  (0x00008000U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_ENDIANESS_SHIFT  (15U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_ENDIANESS_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_ENDIANESS_MAX  (0x00000001U)

#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTKEY_MASK  (0xFFFF0000U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTKEY_SHIFT  (16U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTKEY_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_VECTKEY_MAX  (0x0000ffffU)

#define CSL_CM3NVIC_APPLICATION_INT_AND_RESET_CONTROL_RESETVAL  (0x00000000U)

/* SYSTEM_CONTROL */

#define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPONEXIT_MASK             (0x00000002U)
#define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPONEXIT_SHIFT            (1U)
#define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPONEXIT_RESETVAL         (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPONEXIT_MAX              (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPDEEP_MASK               (0x00000004U)
#define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPDEEP_SHIFT              (2U)
#define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPDEEP_RESETVAL           (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_CONTROL_SLEEPDEEP_MAX                (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_CONTROL_SEVONPEND_MASK               (0x00000010U)
#define CSL_CM3NVIC_SYSTEM_CONTROL_SEVONPEND_SHIFT              (4U)
#define CSL_CM3NVIC_SYSTEM_CONTROL_SEVONPEND_RESETVAL           (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_CONTROL_SEVONPEND_MAX                (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_CONTROL_RESETVAL                     (0x00000000U)

/* CONFIGURATION_CONTROL */

#define CSL_CM3NVIC_CONFIGURATION_CONTROL_NONBASETHRDENA_MASK   (0x00000001U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_NONBASETHRDENA_SHIFT  (0U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_NONBASETHRDENA_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_NONBASETHRDENA_MAX    (0x00000001U)

#define CSL_CM3NVIC_CONFIGURATION_CONTROL_USERSETMPEND_MASK     (0x00000002U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_USERSETMPEND_SHIFT    (1U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_USERSETMPEND_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_USERSETMPEND_MAX      (0x00000001U)

#define CSL_CM3NVIC_CONFIGURATION_CONTROL_UNALIGN_TRP_MASK      (0x00000008U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_UNALIGN_TRP_SHIFT     (3U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_UNALIGN_TRP_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_UNALIGN_TRP_MAX       (0x00000001U)

#define CSL_CM3NVIC_CONFIGURATION_CONTROL_DIV_0_TRP_MASK        (0x00000010U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_DIV_0_TRP_SHIFT       (4U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_DIV_0_TRP_RESETVAL    (0x00000000U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_DIV_0_TRP_MAX         (0x00000001U)

#define CSL_CM3NVIC_CONFIGURATION_CONTROL_BFHFNMIGN_MASK        (0x00000100U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_BFHFNMIGN_SHIFT       (8U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_BFHFNMIGN_RESETVAL    (0x00000000U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_BFHFNMIGN_MAX         (0x00000001U)

#define CSL_CM3NVIC_CONFIGURATION_CONTROL_STKALIGN_MASK         (0x00000200U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_STKALIGN_SHIFT        (9U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_STKALIGN_RESETVAL     (0x00000000U)
#define CSL_CM3NVIC_CONFIGURATION_CONTROL_STKALIGN_MAX          (0x00000001U)

#define CSL_CM3NVIC_CONFIGURATION_CONTROL_RESETVAL              (0x00000000U)

/* SYSTEM_EXCEPTION_PRIORITY_LEVEL */

#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N_MASK  (0x000000FFU)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N_SHIFT  (0U)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N_MAX   (0x000000ffU)

#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N1_MASK  (0x0000FF00U)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N1_SHIFT  (8U)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N1_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N1_MAX  (0x000000ffU)

#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N2_MASK  (0x00FF0000U)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N2_SHIFT  (16U)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N2_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N2_MAX  (0x000000ffU)

#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N3_MASK  (0xFF000000U)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N3_SHIFT  (24U)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N3_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_PRI_N3_MAX  (0x000000ffU)

#define CSL_CM3NVIC_SYSTEM_EXCEPTION_PRIORITY_LEVEL_RESETVAL    (0x00000000U)

/* SYSTEM_HANDLER_CONTROL_AND_STATE */

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTACT_MASK  (0x00000001U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTACT_SHIFT  (0U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTACT_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTACT_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTACT_MASK  (0x00000002U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTACT_SHIFT  (1U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTACT_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTACT_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTACT_MASK  (0x00000008U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTACT_SHIFT  (3U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTACT_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTACT_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCFAULTACT_MASK  (0x00000080U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCFAULTACT_SHIFT  (7U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCFAULTACT_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCFAULTACT_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MONITORACT_MASK  (0x00000100U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MONITORACT_SHIFT  (8U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MONITORACT_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MONITORACT_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_PENDSVACT_MASK  (0x00000400U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_PENDSVACT_SHIFT  (10U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_PENDSVACT_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_PENDSVACT_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SYSICKACT_MASK  (0x00000800U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SYSICKACT_SHIFT  (11U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SYSICKACT_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SYSICKACT_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTPENDED_MASK  (0x00001000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTPENDED_SHIFT  (12U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTPENDED_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTPENDED_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTPENDED_MASK  (0x00002000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTPENDED_SHIFT  (13U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTPENDED_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTPENDED_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTPENDED_MASK  (0x00004000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTPENDED_SHIFT  (14U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTPENDED_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTPENDED_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCALLPENDED_MASK  (0x00008000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCALLPENDED_SHIFT  (15U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCALLPENDED_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_SVCALLPENDED_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTENA_MASK  (0x00010000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTENA_SHIFT  (16U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTENA_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_MEMFAULTENA_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTENA_MASK  (0x00020000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTENA_SHIFT  (17U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTENA_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_BUSFAULTENA_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTENA_MASK  (0x00040000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTENA_SHIFT  (18U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTENA_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_USGFAULTENA_MAX  (0x00000001U)

#define CSL_CM3NVIC_SYSTEM_HANDLER_CONTROL_AND_STATE_RESETVAL   (0x00000000U)

/* CONFIGURABLE_FAULT_STATUS */

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IACCVIOL_MASK     (0x00000001U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IACCVIOL_SHIFT    (0U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IACCVIOL_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IACCVIOL_MAX      (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DACCVIOL_MASK     (0x00000002U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DACCVIOL_SHIFT    (1U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DACCVIOL_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DACCVIOL_MAX      (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MUNSTKERR_MASK    (0x00000008U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MUNSTKERR_SHIFT   (3U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MUNSTKERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MUNSTKERR_MAX     (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MSTKERR_MASK      (0x00000010U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MSTKERR_SHIFT     (4U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MSTKERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MSTKERR_MAX       (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MMARVALID_MASK    (0x00000080U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MMARVALID_SHIFT   (7U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MMARVALID_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_MMARVALID_MAX     (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IBUSERR_MASK      (0x00000100U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IBUSERR_SHIFT     (8U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IBUSERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IBUSERR_MAX       (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_PRECISERR_MASK    (0x00000200U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_PRECISERR_SHIFT   (9U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_PRECISERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_PRECISERR_MAX     (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IMPRECISERR_MASK  (0x00000400U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IMPRECISERR_SHIFT  (10U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IMPRECISERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_IMPRECISERR_MAX   (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNSTKERR_MASK     (0x00000800U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNSTKERR_SHIFT    (11U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNSTKERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNSTKERR_MAX      (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_STKERR_MASK       (0x00001000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_STKERR_SHIFT      (12U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_STKERR_RESETVAL   (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_STKERR_MAX        (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_BFARVALID_MASK    (0x00008000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_BFARVALID_SHIFT   (15U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_BFARVALID_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_BFARVALID_MAX     (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNDEDINSTR_MASK   (0x00010000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNDEDINSTR_SHIFT  (16U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNDEDINSTR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNDEDINSTR_MAX    (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVSTATE_MASK     (0x00020000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVSTATE_SHIFT    (17U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVSTATE_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVSTATE_MAX      (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVPC_MASK        (0x00040000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVPC_SHIFT       (18U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVPC_RESETVAL    (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_INVPC_MAX         (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_NOCP_MASK         (0x00080000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_NOCP_SHIFT        (19U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_NOCP_RESETVAL     (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_NOCP_MAX          (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNALIGNED_MASK    (0x01000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNALIGNED_SHIFT   (24U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNALIGNED_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_UNALIGNED_MAX     (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DIVBYZERO_MASK    (0x02000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DIVBYZERO_SHIFT   (25U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DIVBYZERO_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_DIVBYZERO_MAX     (0x00000001U)

#define CSL_CM3NVIC_CONFIGURABLE_FAULT_STATUS_RESETVAL          (0x00000000U)

/* HARD_FAULT_STATUS */

#define CSL_CM3NVIC_HARD_FAULT_STATUS_VECTBL_MASK               (0x00000002U)
#define CSL_CM3NVIC_HARD_FAULT_STATUS_VECTBL_SHIFT              (1U)
#define CSL_CM3NVIC_HARD_FAULT_STATUS_VECTBL_RESETVAL           (0x00000000U)
#define CSL_CM3NVIC_HARD_FAULT_STATUS_VECTBL_MAX                (0x00000001U)

#define CSL_CM3NVIC_HARD_FAULT_STATUS_FORCED_MASK               (0x40000000U)
#define CSL_CM3NVIC_HARD_FAULT_STATUS_FORCED_SHIFT              (30U)
#define CSL_CM3NVIC_HARD_FAULT_STATUS_FORCED_RESETVAL           (0x00000000U)
#define CSL_CM3NVIC_HARD_FAULT_STATUS_FORCED_MAX                (0x00000001U)

#define CSL_CM3NVIC_HARD_FAULT_STATUS_DEBUGEVT_MASK             (0x80000000U)
#define CSL_CM3NVIC_HARD_FAULT_STATUS_DEBUGEVT_SHIFT            (31U)
#define CSL_CM3NVIC_HARD_FAULT_STATUS_DEBUGEVT_RESETVAL         (0x00000000U)
#define CSL_CM3NVIC_HARD_FAULT_STATUS_DEBUGEVT_MAX              (0x00000001U)

#define CSL_CM3NVIC_HARD_FAULT_STATUS_RESETVAL                  (0x00000000U)

/* DEBUG_FAULT_STATUS */

#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_HALTED_MASK              (0x00000001U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_HALTED_SHIFT             (0U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_HALTED_RESETVAL          (0x00000000U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_HALTED_MAX               (0x00000001U)

#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_BKPT_MASK                (0x00000002U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_BKPT_SHIFT               (1U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_BKPT_RESETVAL            (0x00000000U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_BKPT_MAX                 (0x00000001U)

#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_DWTTRAP_MASK             (0x00000004U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_DWTTRAP_SHIFT            (2U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_DWTTRAP_RESETVAL         (0x00000000U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_DWTTRAP_MAX              (0x00000001U)

#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_VCATCH_MASK              (0x00000008U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_VCATCH_SHIFT             (3U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_VCATCH_RESETVAL          (0x00000000U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_VCATCH_MAX               (0x00000001U)

#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_EXTERNAL_MASK            (0x00000010U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_EXTERNAL_SHIFT           (4U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_EXTERNAL_RESETVAL        (0x00000000U)
#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_EXTERNAL_MAX             (0x00000001U)

#define CSL_CM3NVIC_DEBUG_FAULT_STATUS_RESETVAL                 (0x00000000U)

/* MEMORY_MANAGE_ADDRESS */

#define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS_MMAR_MASK             (0xFFFFFFFFU)
#define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS_MMAR_SHIFT            (0U)
#define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS_MMAR_RESETVAL         (0x00000000U)
#define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS_MMAR_MAX              (0xffffffffU)

#define CSL_CM3NVIC_MEMORY_MANAGE_ADDRESS_RESETVAL              (0x00000000U)

/* BUS_FAULT_MANAGE_ADDRESS */

#define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS_BFAR_MASK          (0xFFFFFFFFU)
#define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS_BFAR_SHIFT         (0U)
#define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS_BFAR_RESETVAL      (0x00000000U)
#define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS_BFAR_MAX           (0xffffffffU)

#define CSL_CM3NVIC_BUS_FAULT_MANAGE_ADDRESS_RESETVAL           (0x00000000U)

/* AUXILIARY_FAULT_STATUS */

#define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS_IMPDEF_MASK          (0xFFFFFFFFU)
#define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS_IMPDEF_SHIFT         (0U)
#define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS_IMPDEF_RESETVAL      (0x00000000U)
#define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS_IMPDEF_MAX           (0xffffffffU)

#define CSL_CM3NVIC_AUXILIARY_FAULT_STATUS_RESETVAL             (0x00000000U)

/* MPU_TYPE */

#define CSL_CM3NVIC_MPU_TYPE_SEPARATE_MASK                      (0x00000001U)
#define CSL_CM3NVIC_MPU_TYPE_SEPARATE_SHIFT                     (0U)
#define CSL_CM3NVIC_MPU_TYPE_SEPARATE_RESETVAL                  (0x00000000U)
#define CSL_CM3NVIC_MPU_TYPE_SEPARATE_MAX                       (0x00000001U)

#define CSL_CM3NVIC_MPU_TYPE_DREGION_MASK                       (0x0000FF00U)
#define CSL_CM3NVIC_MPU_TYPE_DREGION_SHIFT                      (8U)
#define CSL_CM3NVIC_MPU_TYPE_DREGION_RESETVAL                   (0x00000000U)
#define CSL_CM3NVIC_MPU_TYPE_DREGION_MAX                        (0x000000ffU)

#define CSL_CM3NVIC_MPU_TYPE_IREGION_MASK                       (0x00FF0000U)
#define CSL_CM3NVIC_MPU_TYPE_IREGION_SHIFT                      (16U)
#define CSL_CM3NVIC_MPU_TYPE_IREGION_RESETVAL                   (0x00000000U)
#define CSL_CM3NVIC_MPU_TYPE_IREGION_MAX                        (0x000000ffU)

#define CSL_CM3NVIC_MPU_TYPE_RESETVAL                           (0x00000000U)

/* MPU_CONTROL */

#define CSL_CM3NVIC_MPU_CONTROL_ENABLE_MASK                     (0x00000001U)
#define CSL_CM3NVIC_MPU_CONTROL_ENABLE_SHIFT                    (0U)
#define CSL_CM3NVIC_MPU_CONTROL_ENABLE_RESETVAL                 (0x00000000U)
#define CSL_CM3NVIC_MPU_CONTROL_ENABLE_MAX                      (0x00000001U)

#define CSL_CM3NVIC_MPU_CONTROL_HFNMIENA_MASK                   (0x00000002U)
#define CSL_CM3NVIC_MPU_CONTROL_HFNMIENA_SHIFT                  (1U)
#define CSL_CM3NVIC_MPU_CONTROL_HFNMIENA_RESETVAL               (0x00000000U)
#define CSL_CM3NVIC_MPU_CONTROL_HFNMIENA_MAX                    (0x00000001U)

#define CSL_CM3NVIC_MPU_CONTROL_PRIVDEFENA_MASK                 (0x00000004U)
#define CSL_CM3NVIC_MPU_CONTROL_PRIVDEFENA_SHIFT                (2U)
#define CSL_CM3NVIC_MPU_CONTROL_PRIVDEFENA_RESETVAL             (0x00000000U)
#define CSL_CM3NVIC_MPU_CONTROL_PRIVDEFENA_MAX                  (0x00000001U)

#define CSL_CM3NVIC_MPU_CONTROL_RESETVAL                        (0x00000000U)

/* MPU_REGION_NUMBER */

#define CSL_CM3NVIC_MPU_REGION_NUMBER_REGION_MASK               (0x000000FFU)
#define CSL_CM3NVIC_MPU_REGION_NUMBER_REGION_SHIFT              (0U)
#define CSL_CM3NVIC_MPU_REGION_NUMBER_REGION_RESETVAL           (0x00000000U)
#define CSL_CM3NVIC_MPU_REGION_NUMBER_REGION_MAX                (0x000000ffU)

#define CSL_CM3NVIC_MPU_REGION_NUMBER_RESETVAL                  (0x00000000U)

/* MPU_REGION_BASE_ADDRESS */

#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_REGION_MASK         (0x0000000FU)
#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_REGION_SHIFT        (0U)
#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_REGION_RESETVAL     (0x00000000U)
#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_REGION_MAX          (0x0000000fU)

#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_VALID_MASK          (0x00000010U)
#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_VALID_SHIFT         (4U)
#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_VALID_RESETVAL      (0x00000000U)
#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_VALID_MAX           (0x00000001U)

#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_ADDR_MASK           (0xFFFFFF00U)
#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_ADDR_SHIFT          (8U)
#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_ADDR_RESETVAL       (0x00000000U)
#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_ADDR_MAX            (0x00ffffffU)

#define CSL_CM3NVIC_MPU_REGION_BASE_ADDRESS_RESETVAL            (0x00000000U)

/* MPU_REGION_BASE_ATTRIBUTE_AND_SIZE */

#define CSL_CM3NVIC_MPU_REGION_BASE_ATTRIBUTE_AND_SIZE_RESETVAL  (0x00000000U)

/* MPU_ALIAS */

#define CSL_CM3NVIC_MPU_ALIAS_RESETVAL                          (0x00000000U)

/* DEBUG_HALTING_CONTROL_AND_STATUS */

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_DEBUGEN_MASK  (0x00000001U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_DEBUGEN_SHIFT  (0U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_DEBUGEN_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_DEBUGEN_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_HALT_MASK  (0x00000002U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_HALT_SHIFT  (1U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_HALT_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_HALT_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_STEP_MASK  (0x00000004U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_STEP_SHIFT  (2U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_STEP_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_STEP_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_MASKINTS_MASK  (0x00000008U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_MASKINTS_SHIFT  (3U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_MASKINTS_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_MASKINTS_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_SNAPSTALL_MASK  (0x00000020U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_SNAPSTALL_SHIFT  (5U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_SNAPSTALL_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_C_SNAPSTALL_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_REGRDY_MASK  (0x00010000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_REGRDY_SHIFT  (16U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_REGRDY_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_REGRDY_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_HALT_MASK  (0x00020000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_HALT_SHIFT  (17U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_HALT_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_HALT_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_SLEEP_MASK  (0x00040000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_SLEEP_SHIFT  (18U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_SLEEP_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_SLEEP_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_LOCKUP_MASK  (0x00080000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_LOCKUP_SHIFT  (19U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_LOCKUP_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_LOCKUP_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RETIRE_ST_MASK  (0x01000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RETIRE_ST_SHIFT  (24U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RETIRE_ST_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RETIRE_ST_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RESET_ST_MASK  (0x02000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RESET_ST_SHIFT  (25U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RESET_ST_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_S_RESET_ST_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_KEY_MASK   (0xFC000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_KEY_SHIFT  (26U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_KEY_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_KEY_MAX    (0x0000003fU)

#define CSL_CM3NVIC_DEBUG_HALTING_CONTROL_AND_STATUS_RESETVAL   (0x00000000U)

/* DEBUG_CORE_REGISTER_SELECTOR */

#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGSEL_MASK    (0x0000001FU)
#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGSEL_SHIFT   (0U)
#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGSEL_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGSEL_MAX     (0x0000001fU)

#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGWNR_MASK    (0x00010000U)
#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGWNR_SHIFT   (16U)
#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGWNR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_REGWNR_MAX     (0x00000001U)

#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_SELECTOR_RESETVAL       (0x00000000U)

/* DEBUG_CORE_REGISTER_DATA */

#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA_DATA_MASK          (0xFFFFFFFFU)
#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA_DATA_SHIFT         (0U)
#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA_DATA_RESETVAL      (0x00000000U)
#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA_DATA_MAX           (0xffffffffU)

#define CSL_CM3NVIC_DEBUG_CORE_REGISTER_DATA_RESETVAL           (0x00000000U)

/* DEBUG_EXCEPTION_AND_MONITOR_CONTROL */

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CORERESET_MASK  (0x00000001U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CORERESET_SHIFT  (0U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CORERESET_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CORERESET_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_MMERR_MASK  (0x00000010U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_MMERR_SHIFT  (4U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_MMERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_MMERR_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_NOCPERR_MASK  (0x00000020U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_NOCPERR_SHIFT  (5U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_NOCPERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_NOCPERR_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CHKERR_MASK  (0x00000040U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CHKERR_SHIFT  (6U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CHKERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_CHKERR_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_STATERR_MASK  (0x00000080U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_STATERR_SHIFT  (7U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_STATERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_STATERR_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_BUSERR_MASK  (0x00000100U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_BUSERR_SHIFT  (8U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_BUSERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_BUSERR_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_INTERR_MASK  (0x00000200U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_INTERR_SHIFT  (9U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_INTERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_INTERR_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_HARDERR_MASK  (0x00000400U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_HARDERR_SHIFT  (10U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_HARDERR_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_VC_HARDERR_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_EN_MASK  (0x00010000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_EN_SHIFT  (16U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_EN_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_EN_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_PEND_MASK  (0x00020000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_PEND_SHIFT  (17U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_PEND_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_PEND_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_STEP_MASK  (0x00040000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_STEP_SHIFT  (18U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_STEP_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_STEP_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_REQ_MASK  (0x00080000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_REQ_SHIFT  (19U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_REQ_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_MON_REQ_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_TRC_ENA_MASK  (0x01000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_TRC_ENA_SHIFT  (24U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_TRC_ENA_RESETVAL  (0x00000000U)
#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_TRC_ENA_MAX  (0x00000001U)

#define CSL_CM3NVIC_DEBUG_EXCEPTION_AND_MONITOR_CONTROL_RESETVAL  (0x00000000U)

/* SOFTWARE_TRIGGER_INTERRUPT */

#define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT_INTID_MASK       (0x000001FFU)
#define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT_INTID_SHIFT      (0U)
#define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT_INTID_RESETVAL   (0x00000000U)
#define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT_INTID_MAX        (0x000001ffU)

#define CSL_CM3NVIC_SOFTWARE_TRIGGER_INTERRUPT_RESETVAL         (0x00000000U)

/* NVIC_PERIPHERAL_ID_4 */

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4_PERIPHID4_MASK         (0x000000FFU)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4_PERIPHID4_SHIFT        (0U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4_PERIPHID4_RESETVAL     (0x00000004U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4_PERIPHID4_MAX          (0x000000ffU)

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_4_RESETVAL               (0x00000004U)

/* NVIC_PERIPHERAL_ID_5 */

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5_PERIPHID5_MASK         (0x000000FFU)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5_PERIPHID5_SHIFT        (0U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5_PERIPHID5_RESETVAL     (0x00000000U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5_PERIPHID5_MAX          (0x000000ffU)

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_5_RESETVAL               (0x00000000U)

/* NVIC_PERIPHERAL_ID_6 */

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6_PERIPHID6_MASK         (0x000000FFU)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6_PERIPHID6_SHIFT        (0U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6_PERIPHID6_RESETVAL     (0x00000000U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6_PERIPHID6_MAX          (0x000000ffU)

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_6_RESETVAL               (0x00000000U)

/* NVIC_PERIPHERAL_ID_7 */

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7_PERIPHID7_MASK         (0x000000FFU)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7_PERIPHID7_SHIFT        (0U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7_PERIPHID7_RESETVAL     (0x00000000U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7_PERIPHID7_MAX          (0x000000ffU)

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_7_RESETVAL               (0x00000000U)

/* NVIC_PERIPHERAL_ID_0 */

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0_PERIPHID0_MASK         (0x000000FFU)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0_PERIPHID0_SHIFT        (0U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0_PERIPHID0_RESETVAL     (0x00000000U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0_PERIPHID0_MAX          (0x000000ffU)

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_0_RESETVAL               (0x00000000U)

/* NVIC_PERIPHERAL_ID_1 */

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1_PERIPHID1_MASK         (0x000000FFU)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1_PERIPHID1_SHIFT        (0U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1_PERIPHID1_RESETVAL     (0x000000b0U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1_PERIPHID1_MAX          (0x000000ffU)

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_1_RESETVAL               (0x000000b0U)

/* NVIC_PERIPHERAL_ID_2 */

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2_PERIPHID2_MASK         (0x000000FFU)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2_PERIPHID2_SHIFT        (0U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2_PERIPHID2_RESETVAL     (0x0000002bU)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2_PERIPHID2_MAX          (0x000000ffU)

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_2_RESETVAL               (0x0000002bU)

/* NVIC_PERIPHERAL_ID_3 */

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3_PERIPHID3_MASK         (0x000000FFU)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3_PERIPHID3_SHIFT        (0U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3_PERIPHID3_RESETVAL     (0x00000000U)
#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3_PERIPHID3_MAX          (0x000000ffU)

#define CSL_CM3NVIC_NVIC_PERIPHERAL_ID_3_RESETVAL               (0x00000000U)

/* NVIC_COMPONENT_ID_0 */

#define CSL_CM3NVIC_NVIC_COMPONENT_ID_0_PCELLID0_MASK           (0x000000FFU)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_0_PCELLID0_SHIFT          (0U)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_0_PCELLID0_RESETVAL       (0x0000000dU)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_0_PCELLID0_MAX            (0x000000ffU)

#define CSL_CM3NVIC_NVIC_COMPONENT_ID_0_RESETVAL                (0x0000000dU)

/* NVIC_COMPONENT_ID_1 */

#define CSL_CM3NVIC_NVIC_COMPONENT_ID_1_PCELLID1_MASK           (0x000000FFU)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_1_PCELLID1_SHIFT          (0U)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_1_PCELLID1_RESETVAL       (0x000000e0U)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_1_PCELLID1_MAX            (0x000000ffU)

#define CSL_CM3NVIC_NVIC_COMPONENT_ID_1_RESETVAL                (0x000000e0U)

/* NVIC_COMPONENT_ID_2 */

#define CSL_CM3NVIC_NVIC_COMPONENT_ID_2_PCELLID2_MASK           (0x000000FFU)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_2_PCELLID2_SHIFT          (0U)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_2_PCELLID2_RESETVAL       (0x00000005U)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_2_PCELLID2_MAX            (0x000000ffU)

#define CSL_CM3NVIC_NVIC_COMPONENT_ID_2_RESETVAL                (0x00000005U)

/* NVIC_COMPONENT_ID_3 */

#define CSL_CM3NVIC_NVIC_COMPONENT_ID_3_PCELLID3_MASK           (0x000000FFU)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_3_PCELLID3_SHIFT          (0U)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_3_PCELLID3_RESETVAL       (0x000000b1U)
#define CSL_CM3NVIC_NVIC_COMPONENT_ID_3_PCELLID3_MAX            (0x000000ffU)

#define CSL_CM3NVIC_NVIC_COMPONENT_ID_3_RESETVAL                (0x000000b1U)

#ifdef __cplusplus
}
#endif
#endif
